Generally, electronic design automation (EDA) tools assist semiconductor designers to take a purely behavioral description of a desired circuit and work to fashion a finished layout of the circuit ready to be manufactured. This process usually takes the behavioral description of the circuit and turns it into a functional description, which is then decomposed into thousands of Boolean functions and mapped into rows of cells using a standard cell library. Once mapped, a synthesis is performed to turn the structural design into a physical layout.
However, as semiconductor devices in general become smaller and smaller, technical problems have arisen within the field of electronic design automation. Such issues can arise when structural designs reach the physical limitations of the manufacturing processes that will be used to turn the designs into the physical semiconductor device. Such problems need to be addressed and overcome in order to continue to reduce the overall size of the semiconductor devices.